Current interconnection technologies conventionally use tungsten or polysilicon to make contacts to devices and also to act as a short local interconnect lines. These local interconnect lines are then joined to high conductivity interconnection lines (say M.sub.1) on a higher plane through tungsten via-plugs. The local interconnects are separated from the M.sub.1 layer usually by a layer of phospho-silicate glass (PSG).
The via-interconnection between the first high conductivity metal lines (M.sub.1) and the next level of high conductivity metal lines (say M.sub.2) is preferably made with the same high conductivity metal instead of tungsten.
Various other schemes for multilevel interconnection, and more particularly for utilization of a composite insulator, are taught in the prior art.
U.S. Pat. No. 3,837,907 (Berglund et al.) and U.S. Pat. No. 4,309,812 (Horng et al.) use a scheme, where composite insulators with different etching characteristics are used to make an overhung structure of insulator layers in order to reduce the spacing between the adjacent features. Berglund uses this scheme to reduce the spacing between the adjacent interconnect metal lines. However, this scheme is limited to metal lines running in any one particular direction which reduces its applicability.
U.S. Pat. No. 4,309,812 (Horng et al.), assigned to the instant assignee, and the disclosure of which is incorporated herein by reference, uses the above scheme to make closely spaced device contacts.
U.S. Pat. No. 5,326,426 (Tam et al.) utilize layers of different insulating material to provide a reflective coating for a laser mask.
U.S. Pat. No. 5,403,779 (Joshi et al.), assigned to the instant assignee, and the disclosure of which is incorporated herein by reference, teaches use of an organic dielectric layer sandwiched between inorganic dielectric layers.
It is well within the experience of artisans in this field that chemical/mechanical polishing of an organic layer produces debris thereby causing defects like metal opens and holes in the next level of dielectric.
U.S. Pat. No. 5,404,635 (Das) teaches use of a single dielectric layer to act as a spacer and an etch stop to fabricate thin film magnetic head.
U.S. Pat. No. 5,252,516 (Nguyen et al.), assigned to the assignee of the instant invention and the disclosure of which is incorporated herein by reference, teaches the use of a composite insulator comprised of a relatively thick layer of a reactively ion etchable dielectric and covered with a thin layer of an dielectric resistant to reactive etching.
U.S. Pat. No. 5,466,639 (Ireland), teaches double mask process for forming trenches and contacts during the formation of a semiconductor memory device. He shows another application of composite insulator to sequentially etch dielectric for the purpose of double damascene. Ireland uses a set of 3 dielectric layers to make cavity which consists of via stud and line patterns. However, the combination of three distinct layers of insulators causes charge trapment and dielectric losses.
U.S. Pat. No. 5,518,963 (Park), discloses a method for forming metal interconnection of semiconductor device. He uses insulating layer to etch a hole in one insulator while the second insulator protects the metal underneath from exposure to harsh etchants of the first insulator.
Artisans in the field of semiconductor integrated circuits are cognizant that multiple dielectric layers not only cause process complications and cost increase but more significantly it impedes the device functionality due to increased capacitance.
Thus, despite repeated efforts, and various schemes in the prior art, problems of leakage, short circuits, process yield, electromigration failure etc., remain and better methods, necessarily with simpler and fewer process steps, for making an integrated circuit pattern need to be developed.